This invention relates generally to computer systems and components and specifically to a method and apparatus for transmitting control information across a serialized bus interface.
Computer system architectures are typically designed with standardized busses that can include slots. Various devices can be coupled to the system via these slots. Examples of standardized busses include the Peripheral Component Interface (PCI) bus, the Industry Standard Architecture (ISA) bus and the Extended Industry Standard Architecture (EISA) bus.
FIG. 1 illustrates a block diagram of a conventional computer system 10. Processor 12 may be an x86 compatible microprocessor such as the Pentium (II or III) available from Intel Corporation or the equivalent processor (e.g., K6 or K7) available from Advanced Micro Devices.
The processor 12 is coupled to a processor bus 14, which is typically proprietary (e.g., not standardized) to the processor 12. The bus 14 is coupled to a memory system 16. The memory system 16 includes dynamic random access memory (DRAM) as well as associated control circuitry.
Processor bus 14 is also coupled to a PCI bus 20 through a bridge circuit 18, often referred to as a north bridge. In some instances, the memory control circuitry from memory system 16 and the bridge circuitry are combined in a single chip. In this case, not illustrated, the north bridge 18 would be coupled between processor 12 and memory 16.
PCI bus 20 includes a number of slots 22 that can be used to couple various devices to the bus. For example, the slots could be used to coupled devices such as hard disk drives, modems, network interface cards, optical drives (e.g., CD ROM or DVD), or other devices.
PCI bus 20 is coupled to a legacy bus, typically an ISA or EISA bus 26, through a second bridge circuit 24, often referred to as a south bridge. The (E)ISA bus 26 includes slots 28 typically used for input/output devices such as the keyboard, mouse, display and other devices such as the non-volatile memory.
The PCI bus 20 is a standardized bus and therefore can include only a limited number of slots 22. If more slots are needed, a second PCI bus 32 can be coupled to the first PCI bus 20 through a PCI-to-PCI bridge circuit (P2P) 30. In this configuration, the PCI bus 20 coupled to the north bridge is referred to as the primary PCI bus and the second PCI bus 32 is referred to as the secondary PCI bus. The secondary PCI bus 32 includes slots 34 that can be utilized in the same manner as slots 22. In fact, from the perspective of an operating system being executed on processor 12 primary PCI bus 20 and secondary PCI bus 32 appear to be a single PCI bus.
The preferred embodiment present invention provides a scheme that can be used to transmit control signal from one parallel bus to a second parallel bus over a serial link. While not limited to a single type of system, the preferred embodiment of the present invention was developed initially in the context of a PCI-to-PCI bridge that includes a serial link. This type of configuration provides advantages in a number of situations such as when the secondary PCI bus is separated from the primary PCI bus.
A serial PCI-to-PCI bridge is different from a conventional PCI-to-PCI bridge in the respect that it has a serial link between the two PCI interfaces. Each PCI interface is typically a separate entity or a separate chip. Both the interface chips can communicate between them in two modes of operation through the serial link. One problem addressed by the preferred embodiment involves resetting the secondary PCI interface device and another is initializing both the parts to the same mode so that they can start communicating data between them.
In one aspect, the present invention discloses a bus interface device includes a parallel input configured to be coupled to a bus, such as a primary PCI bus. The device also includes a parallel data output and at least two control output nodes. Data control circuitry coupled to the control output nodes utilizes a coding scheme (e.g., an 8B/10B scheme) to generate one of a set of control codes (e.g., Idle, Extend, Normal Data and Error) to be provided to the control output nodes. The device also includes reset control circuitry that generates a specified sequence of control codes (e.g., a sequence of Idle""s and Extend""s) on the control outputs. This sequence can be used to communicate information such as a signal (e.g., reset signal) and/or a mode (e.g., a CRC mode).
The device can be used in a computer system, such as for communicating from a processor to a peripheral device. For example, the device can be used to transmit a reset signal from a processor to a remote PCI bus. The processor would communicate an indication that the system is being reset along at least one line of a parallel bus, e.g., a primary PCI bus. The indication would be received at a first interface device and communicated along a serial link using control codes of an encoding/decoding scheme of the interface device. The indication would then be received at a second interface device, which may in turn be coupled to a second parallel bus such as a secondary PCI bus.